Before learning Assembly, I think it would be useful to learn a bit about different components of CPU in general. If we think of CPU as a black box its main function is to fetch instructions from RAM which are in the form of machine code and execute them.

Components of CPU

  1. Arithmetic Logic Unit (ALU)
  2. Memory Management Unit (MMU)
  3. Control Unit (CU)
  4. Registers
  5. Clock
  6. Cache
  7. Buses

1. Arithmetic Logic Unit (ALU)

ALU is an electronic circuit made of NAND gates responsible for performing arithmetic and logical operations on integer binary numbers. It takes two operands as inputs and an opcode to indicate the type of operation to be performed. Operations supported by ALU are Add, Subtract, Negation, Two’s complement, AND, OR, XOR, bit shift, etc.

2. Memory Management Unit (MMU)

The primary function of the MMU is to translate virtual addresses generated by the CPU into physical addresses used by the underlying hardware memory. It acts as a bridge between CPU and RAM, managing how the CPU accesses data stored in memory and provides an illusion of infinite memory space for programs. MMU utilizes different stragies such as the branch and bound registers, segmentation, page tables, TLB’s, etc to facilitate address translation.

3. Control Unit (CU)

CU’s primary function is to direct the operations of the CPU by interpreting instructions and generating control signals to execute them.

  1. Instruction Fetching:
    • The CU fetches instructions from the memory unit (RAM) based on the Program Counter (PC) value.
    • It reads the instruction from memory and stores it temporarily in the Instruction Register (IR) for decoding.
  2. Instruction Decoding:
    • The CU interprets the fetched instruction from the IR.
    • It breaks down the instruction into its constituent parts (opcode, operands) and sends control signals to other CPU components.
  3. Operand Fetching:
    • If the instruction requires operands from memory or registers, the CU initiates the necessary data transfers.
    • It interacts with the memory address register (MAR) and memory data register (MDR) to fetch data from memory.
  4. Execution Control:
    • The CU generates control signals to coordinate the execution of the instruction.
    • It activates specific functional units within the CPU, such as the ALU, to perform arithmetic, logic, or data manipulation operations.
  5. Exception Handling:
    • The CU detects and handles exceptions, interrupts, or other abnormal conditions that occur during program execution.
    • It may suspend the current instruction stream, save the current CPU state, and transfer control to an appropriate exception handler routine.
  6. Synchronization and Control:
    • The CU synchronizes the activities of different CPU components and ensures that instructions are executed in the correct sequence.
    • It generates timing signals, clock pulses, and control signals to coordinate the operation of the CPU and maintain system integrity.

Purpose of IR, MAR and MDR registers

Instruction Register (IR):

  • After fetching an instruction from memory, the CPU places it into the IR for decoding and execution.
  • The CU (Control Unit) interacts with the IR to decode the instruction and generate control signals for its execution.

Memory Address Register (MAR):

  • When the CPU needs to read or write data or instructions from/to memory, it places the memory address into the MAR to specify the location in memory.
  • The CU interacts with the MAR when initiating memory read or write operations. It provides the memory address to the MAR, which is used to access the desired location in memory.

Memory Data Register (MDR):

  • When the CPU reads data from memory, it is stored temporarily in the MDR before being processed further. Similarly, when the CPU writes data to memory, it places the data into the MDR before it is transferred to the memory module.
  • The CU interacts with the MDR during memory read or write operations. After fetching data from memory (or before writing data to memory), the data is transferred between the MDR and the CPU’s internal registers for processing.

4. Registers

Registers are small, fast storage locations within the CPU that hold data and instructions temporarily during processing.

Types of Registers

  1. General-Purpose Registers (GPRs):
    • Used to store temporary data and intermediate results during computation.
    • In x86 architecture, common GPRs include EAX, EBX, ECX, and EDX.
  2. Special-Purpose Registers
    • Program Counter (PC): Holds the address of the next instruction to be executed.
    • Instruction Register (IR): Holds the current instruction being decoded and executed.
    • Memory Address Register (MAR): Holds the memory address of data that needs to be accessed.
    • Memory Data Register (MDR): Holds the data fetched from or to be written to memory.
    • Instruction Register (IR): Holds the current instruction to be executed.
  3. Index and Base Registers
    • Used for addressing modes, particularly in complex addressing calculations like indexed and based addressing.
  4. Stack Pointer (SP) and Base Pointer (BP)
    • Used for stack operations. The SP points to the top of the stack, and the BP is often used to reference the base of the stack frame.

5. Clock

CPU clocks generates regular electrical pulses known as clock cycleswhich synchronize the operations of the CPU and other components in the computer system. Synchronization ensures that tasks are performed in the correct order and at the right times, enabling the smooth and efficient execution of instructions.

  • The clock synchronizes the activities of various components within the CPU, such as the Control Unit (CU), Arithmetic Logic Unit (ALU), registers, and memory interfaces.
  • Each stage of the instruction cycle (fetch, decode, execute, and write-back) is typically completed in one or more clock cycles, depending on the complexity of the instruction and the CPU architecture.

6. Cache

Cache in a CPU is a small, high-speed memory located inside the CPU or very close to it. Its main purpose is to temporarily store copies of frequently accessed data from the main memory (RAM), reducing the time it takes for the CPU to access this data.

The cache is significantly faster than the main memory (RAM). It’s built with a special type of memory called Static Random-Access Memory (SRAM), which offers much faster access times compared to the Dynamic Random-Access Memory (DRAM) used in RAM.

Types of CPU Cache

  1. L1 Cache (Level 1)
    • Typically located directly on the CPU chip.
    • Smallest in size, ranging from a few kilobytes to tens of kilobytes.
  2. L2 Cache (Level 2)
    • Larger than L1, ranging from tens of kilobytes to a few megabytes, often shared between multiple CPU cores.
  3. L3 Cache (Level 3)
    • Largest and slowest cache, shared by all CPU cores in a multi-core processor.

7. Buses

In a CPU and computer system, buses are communication pathways that transfer data between different components. These buses are critical for ensuring that data, control signals, and power are efficiently moved within the CPU and between the CPU and other parts of the computer.

Types of Buses

  1. Data Bus
    • Transfers data between the CPU, memory, and other peripherals.
    • The width of the data bus (e.g., 8-bit, 16-bit, 32-bit, 64-bit) determines how much data can be transferred simultaneously. For example, a 32-bit data bus can transfer 32 bits of data at a time.
    • Typically bidirectional, allowing data to be read from and written to memory or peripherals.
  2. Address Bus
    • Carries addresses from the CPU to memory and other peripherals, indicating where data should be read from or written to.
    • The width of the address bus determines the maximum addressable memory. For example, a 32-bit address bus can address 232 unique locations.
    • Unidirectional, as addresses are only sent from the CPU to other components.
  3. Control Bus
    • Carries control signals from the CPU to other components to coordinate and manage their operations.
    • Control signals indicate whether data is to be read or written, when to start or stop an operation, and other control functions like interrupt requests.
    • Typically bidirectional, as control signals can flow to and from the CPU.

Examples of Buses in CPU Systems

  1. Front-Side Bus (FSB)
    • Connects the CPU to the main memory (RAM) and the chipset.
    • Historically, the FSB was the main pathway for data communication between the CPU and memory. Modern systems often use more complex architectures like Direct Media Interface (DMI) or HyperTransport.
  2. Back-Side Bus (BSB)
    • Connects the CPU to the L2 or L3 cache.
    • The BSB allows for high-speed communication between the CPU and its cache, improving performance.
  3. System Bus
    • Combines the data, address, and control buses into a single bus that connects the CPU to memory and peripherals.
    • This bus is used for general communication across the system, ensuring all components can interact as needed.
  4. Peripheral Component Interconnect (PCI) Bus
    • Connects peripheral devices to the CPU.
    • The PCI bus allows the CPU to communicate with hardware devices like network cards, sound cards, and graphics cards.