<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/"><channel><title>Memory-Coalescing on Sanketh's Blog</title><link>https://sankethbk.github.io/blog/tags/memory-coalescing/</link><description>Recent content in Memory-Coalescing on Sanketh's Blog</description><generator>Hugo -- 0.166.0</generator><language>en-us</language><lastBuildDate>Sun, 30 Aug 2026 00:00:00 +0000</lastBuildDate><atom:link href="https://sankethbk.github.io/blog/tags/memory-coalescing/index.xml" rel="self" type="application/rss+xml"/><item><title>CUDA Memory Coalescing: Why Access Patterns Matter</title><link>https://sankethbk.github.io/blog/posts/gpu/2026-08-30-3-cuda-memory-coalescing/</link><pubDate>Sun, 30 Aug 2026 00:00:00 +0000</pubDate><guid>https://sankethbk.github.io/blog/posts/gpu/2026-08-30-3-cuda-memory-coalescing/</guid><description>&lt;h1 id="cuda-memory-coalescing-why-access-patterns-matter"&gt;CUDA Memory Coalescing: Why Access Patterns Matter&lt;/h1&gt;
&lt;p&gt;The &lt;a href="https://sankethbk.github.io/blog/gpu/2026-08-30-2-cuda-programming-model"&gt;previous note&lt;/a&gt; showed how to write and launch a CUDA kernel. This note answers the first performance question: why does the same kernel sometimes run 5× or 10× slower just because of how threads read memory?&lt;/p&gt;
&lt;p&gt;The answer is &lt;strong&gt;memory coalescing&lt;/strong&gt;. Because GPU memory is optimized for bandwidth over latency, the hardware rewards access patterns where threads in a warp read or write contiguous addresses together. If they do not, the GPU wastes bandwidth and cycles fetching data that most threads ignore.&lt;/p&gt;</description></item></channel></rss>