<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/"><channel><title>Shared-Memory on Sanketh's Blog</title><link>https://sankethbk.github.io/blog/tags/shared-memory/</link><description>Recent content in Shared-Memory on Sanketh's Blog</description><generator>Hugo -- 0.166.0</generator><language>en-us</language><lastBuildDate>Tue, 01 Sep 2026 00:00:00 +0000</lastBuildDate><atom:link href="https://sankethbk.github.io/blog/tags/shared-memory/index.xml" rel="self" type="application/rss+xml"/><item><title>CUDA Shared Memory Tiling</title><link>https://sankethbk.github.io/blog/posts/gpu/2026-09-01-1-cuda-shared-memory-tiling/</link><pubDate>Tue, 01 Sep 2026 00:00:00 +0000</pubDate><guid>https://sankethbk.github.io/blog/posts/gpu/2026-09-01-1-cuda-shared-memory-tiling/</guid><description>&lt;h1 id="cuda-shared-memory-tiling"&gt;CUDA Shared Memory Tiling&lt;/h1&gt;
&lt;p&gt;The &lt;a href="https://sankethbk.github.io/blog/gpu/2026-08-30-3-cuda-memory-coalescing"&gt;previous note&lt;/a&gt; showed that coalesced memory access is the key to memory-bound kernel performance. But some algorithms naturally want uncoalesced access patterns. The fix is &lt;strong&gt;shared-memory tiling&lt;/strong&gt;: load data into fast on-chip SRAM in a coalesced way, rearrange it there, then write it back to global memory in a coalesced way.&lt;/p&gt;
&lt;p&gt;This note explains the tiling pattern, why &lt;code&gt;__syncthreads()&lt;/code&gt; is essential, the bank-conflict problem, and how to choose tile sizes.&lt;/p&gt;</description></item></channel></rss>